1. Field of Invention
The present invention relates to in general a switching mode audio power amplifier and, more particularly, to circuits and methods for power Vcc/Ground overshoot/undershoot prevention and slew rate control in switching mode circuits and systems.
2. Description of Related Art
Class D audio power amplifier is one type of switching circuit. Therefore, Class D audio power amplifier is chosen for illustration purpose. Most of the audio power amplifiers in the market are based on Class AB amplifier. This architecture offers very good total harmonic distortion plus noise (THD+N) performance, with fairly low quiescent current. However, the Class AB push-pull amplifiers are very inefficient and can only achieve an efficiency of about 60%, which results in not only power loss, but also additional bulky heatsink attached to the power amplifiers.
One major advantage of Class D amplifiers is the efficiency, which could reach above 90%. The high efficiency is achieved by full signal swing at power transistors. A typical Class D amplifier circuit 1000 is shown in FIG. 1, which includes a pulse width modulator 1010, an upper level shifter 1020, a lower level shifter 1030, a first pair of complementary transistors M30 and M40, which drives a first MOSFET switch M10, and a second pair of complementary transistors M50 and M60, which drives a second MOSFET switch M20.
Due to the large transistor size of power transistors, the gate parasitic capacitance is large. In case wire path from power transistors to power supply or power ground is long, the parasitic inductance originated from these wires is large. The bonding wires from connecting power supply pads and power supply pin and bonding wires connecting power ground pads and power ground pin are also long, the parasitic inductance originated from these wires is also large. These parasitic effects are demonstrated in FIG. 1 as CG10, CG20, L10 and L20. In the actual operation of Class D amplifier circuit 1000, in case of heavy load, large current is flowing through power transistor M10 and M20 in a complementary way. Let us just take L20 as an example. From physics equation, we know the voltage across PGND and DGND can be expressed as:
      V    ⁡          (              PGND        -        DGND            )        =            L      20        *                  ⅆ        i                    ⅆ        t            In case the circuit is heavily loaded, large switching current is flowing through lower power transistor M20. If M20 is turned off in a very short period, this large current is turned off as well. From above equation, we can predict that a large negative voltage is generated during this short period at power ground. For example, parasitic inductance L20 is assumed to be 0.1 nH, 10A current is turned off within a period of 1 ns, therefore,
      V    ⁡          (              PGND        -        DGND            )        =            0.1      ×              10                  -          9                    *                        -          10                          1          ×                      10                          -              9                                            =                  -        1            ⁢                          ⁢      V      It indicates that due to parasitic inductance on power ground wire, an undershoot voltage at power ground occurs with respect to digital ground when large current is quickly turned off at lower power transistor. FIGS. 5A and 5B show power ground undershoot in relation to fast slew rate of gate voltage of lower power transistor.
Undershoot at power ground causes noise, instability of the whole Class D amplifier circuit. Even worse, the Class D amplifier circuit is prone to latch-up when undershoot at power ground is large.
By observing the above equation, it is noticed that undershoot voltage at power ground is determined by 3 factors: parasitic inductance of power ground wire, current level at peak load and turn-off time of lower power transistor. To reduce undershoot at power ground, parasitic inductance of power ground wire can be reduced by increasing power ground wire width and shorten its length. However, this method increases chip size and its effect on parasitic inductance is not as significant as desired. Current level at peak load is a customer-defined parameter, which is not within the control of circuit designer. Turn-off time of lower power transistor is determined by parasitic gate capacitance of lower power transistor M20 and the size of discharging transistor M60. Parasitic gate capacitance CG20 is defined by customer-defined parameter efficiency and fabrication process, which is also not within the control of circuit designer. However discharging transistor M60 can be replaced with a self-adjusted discharging circuit, whose discharging speed is controlled by power ground voltage level. In other words, the slew rate of gate voltage at lower power transistor is controlled so that undershoot voltage at power ground is minimized.